The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to wrap-around contacts for field-effect transistors (FETs) and their fabrication.
With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The contribution of middle-of-line (MOL) contact resistance to the total parasitic resistance is increasing due to aggressive dimensional scaling in advanced CMOS devices. Silicide/source-drain interface resistance can be a major contributor to the total external parasitic resistance. Increasing silicide contact length by wrapping around the total source-drain surface can reduce the overall contact resistance. Conformal metallization processes using chemical vapor deposition (CVD) or atomic layer deposition (ALD) are known to the art. The delivery of dopants to source-drain regions has been effected through the use of plasma-based doping techniques. It is challenging to deliver dopants uniformly around epitaxially formed source-drain structures using such techniques. Faceted, epitaxially grown source-drain structures are found in various field-effect transistor architectures including tri-gate FinFETs and nanosheet field-effect transistors.
Nanosheet FETs may include multiple channel layers, each channel layer being separated by a gate stack including a layer of electrically conductive gate material and a gate dielectric layer. The gate stacks wrap around all sides of the channel layers, thereby forming a gate-all-around (GAA) structure. Epitaxial regions on the ends of the nanosheet channel layers form source/drain regions of the nanosheet FETs.
Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor such as the source/drain regions, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.
Source/drain extension regions of FinFETs can be formed after the disposable gate structures have been completed. Such extension regions are grown epitaxially and comprise faceted structures. A planarization dielectric layer is deposited over the semiconductor substrate, the disposable gate structures, and the gate spacers. The planarization dielectric layer may include a dielectric material that can be planarized, for example, by chemical mechanical planarization (CMP). For example, the planarization dielectric layer can include a doped silicate glass, an undoped silicate glass (silicon oxide), and/or porous or non-porous organosilicate glass. The planarization dielectric layer is planarized above the topmost surfaces of the disposable gate structures.
The disposable gate structures are removed by at least one etch that is selective to the gate spacers and to the dielectric materials of the planarization dielectric layer. Cavities are formed from the spaces remaining after the disposable gate structures are removed. The semiconductor surfaces above the channel regions of the substrate can be physically exposed at the bottoms of the gate cavities, though native oxide layers may be present. The gate cavities are laterally enclosed by the gate spacers that were formed on the sidewalls of the disposable structures. Replacement gate structures are ordinarily formed in the gate cavities. MOL processing includes the formation of source-drain contacts.